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    Difference between revisions of "intel/xeon e3/e3-1220 v5"    
                	
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| |bandwidth dchan=35.76 GiB/s | |bandwidth dchan=35.76 GiB/s | ||
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| == Expansions == | == Expansions == | ||
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| | pcie revision      = 3.0 | | pcie revision      = 3.0 | ||
| | pcie lanes         = 16 | | pcie lanes         = 16 | ||
| | pcie config        = 1x16 | | pcie config        = 1x16 | ||
| − | | pcie config  | + | | pcie config 2      = 2x8 | 
| − | | pcie config  | + | | pcie config 3      = 1x8+2x4 | 
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| + | == Graphics == | ||
| + | This chip has no integrated graphics processing unit. | ||
| == Features ==   | == Features ==   | ||
Revision as of 10:57, 3 June 2017
Template:mpu Xeon E3-1220 V5 is an entry-level server and workstation 64-bit quad-core x86 microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3 GHz with turbo boost of 3.5 GHz. The E3-1220 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.
Cache
- Main article: Skylake § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||||||||||||||
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Memory controller
|  | Integrated Memory Controller | |||||||||||||
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Expansions
|  | Expansion Options | |||||||
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Graphics
This chip has no integrated graphics processing unit.
Features
Facts about "Xeon E3-1220 v5  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1220 v5 - Intel#io + | 
| has ecc memory support | true + | 
| l1$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + | 
| l3$ description | 16-way set associative + | 
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + | 
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 16 + | 
| supported memory type | DDR3L-1600 + and DDR4-2133 + |