Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon platinum/8168"
| Line 130: | Line 130: | ||
|l3 cache=33 MiB | |l3 cache=33 MiB | ||
|l3 break=24x1.375 MiB | |l3 break=24x1.375 MiB | ||
| − | |l3 desc= | + | |l3 desc=11-way set associative |
|l3 policy=write-back | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 08:46, 4 June 2017
Template:mpu Xeon Platinum 8168 is a 64-bit x86 high-performance server tetracosa-core multiprocessor set to be introduced by Intel in the second quarter of 2017. This processor is based on the server configuration of the Skylake microarchitecture (a Skylake SP core) and is manufactured on Intel's 14 nm process. The 8168 operates at 2.7 GHz.
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||
|
||||||||||||
Facts about "Xeon Platinum 8168 - Intel"
| has ecc memory support | true + |
| l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + |
| max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
| max memory channels | 6 + |
| supported memory type | DDR4-2666 + |