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Difference between revisions of "intel/core i7/i7-8550u"
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{{intel title|Core i7-8550U}}
 
{{intel title|Core i7-8550U}}
 
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| future              = Yes
 
| name                = Core i7-8550U
 
| name                = Core i7-8550U
 
| no image            = Yes
 
| no image            = Yes
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}}
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'''Core i7-8550U''' is a {{arch|64}} [[quad-core]] performance [[x86]] mobile microprocessor set to be introduced by [[Intel]] in mid-[[2017]]. This processor, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is manufactured on Intel's 3rd generation enhanced [[14 nm process|14nm+ process]]. The i7-8550U operates at ? GHz with a TDP of 15 W and with a {{intel|Turbo Boost}} frequency of ? GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.
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{{unknown features}}
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== Cache ==
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{{main|intel/microarchitectures/coffee_lake#Memory_Hierarchy|l1=Coffee Lake § Cache}}
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{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
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|l1i desc=8-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
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|l2 cache=1 MiB
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|l2 break=4x256 KiB
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|l2 desc=4-way set associative
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|l2 policy=write-back
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|l3 cache=8 MiB
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|l3 break=4x2 MiB
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|l3 desc=16-way set associative
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|l3 policy=write-back
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}}
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== Memory controller ==
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{{memory controller
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|type=LPDDR3-1866
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|type 2=DDR3L-1600
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|type 3=DDR4-2133
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|ecc=No
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|max mem=32 GiB
 +
|controllers=1
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|channels=2
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|max bandwidth=31.79 GiB/s
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|bandwidth schan=15.89 GiB/s
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|bandwidth dchan=31.79 GiB/s
 +
}}
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== Expansions ==
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{{expansions
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| pcie revision      = 3.0
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| pcie lanes        = 12
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| pcie config        = 1x4
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| pcie config 2      = 2x2
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| pcie config 3      = 1x2+2x1
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| pcie config 4      = 4x1
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}}
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== Graphics ==
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{{empty section}}
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== Features ==
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{{x86 features
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|real=Yes
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|protected=Yes
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|smm=Yes
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|fpu=Yes
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|x8616=Yes
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|x8632=Yes
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|x8664=Yes
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|nx=Yes
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|3dnow=No
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|e3dnow=No
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|mmx=Yes
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|emmx=Yes
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|sse=Yes
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|sse2=Yes
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|sse3=Yes
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|ssse3=Yes
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|sse41=Yes
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|sse42=Yes
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|sse4a=No
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|avx=Yes
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|avx2=Yes
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|avx512=No
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|abm=Yes
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|tbm=No
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|bmi1=Yes
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|bmi2=Yes
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|fma3=Yes
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|fma4=No
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|aes=Yes
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|rdrand=Yes
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|sha=No
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|xop=No
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|adx=Yes
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|clmul=Yes
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|f16c=Yes
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|tbt1=No
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|tbt2=Yes
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|tbmt3=No
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|bpt=No
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|eist=Yes
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|sst=Yes
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|flex=Yes
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|fastmem=No
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|isrt=Yes
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|sba=No
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|mwt=Yes
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|sipp=No
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|att=No
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|ipt=No
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|tsx=No
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|txt=No
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|ht=Yes
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|vpro=No
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|vtx=Yes
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|vtd=Yes
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|ept=Yes
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|mpx=Yes
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|sgx=Yes
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|securekey=Yes
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|osguard=Yes
 +
|smartmp=No
 +
|powernow=No
 +
|amdv=No
 +
|rvi=No
 
}}
 
}}

Revision as of 08:27, 26 May 2017

Template:mpu Core i7-8550U is a 64-bit quad-core performance x86 mobile microprocessor set to be introduced by Intel in mid-2017. This processor, which is based on the Coffee Lake microarchitecture, is manufactured on Intel's 3rd generation enhanced 14nm+ process. The i7-8550U operates at ? GHz with a TDP of 15 W and with a Turbo Boost frequency of ? GHz for a single active core. This MPU supports up to 32 GiB of dual-channel non-ECC DDR4-2133 memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Coffee Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR3-1866, DDR3L-1600, DDR4-2133
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes12
Configs1x4, 2x2, 1x2+2x1, 4x1


Graphics

New text document.svg This section is empty; you can help add the missing info by editing this page.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access
ISRTSmart Response Technology
MWTMy WiFi Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/core_i7/i7-8550u&oldid=43163"
Facts about "Core i7-8550U - Intel"
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Core i7-8550U - Intel#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology +
has intel enhanced speedstep technologytrue +
has intel flex memory access supporttrue +
has intel my wifi technology supporttrue +
has intel secure key technologytrue +
has intel smart response technology supporttrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel turbo boost technology 2 0true +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes12 +
supported memory typeLPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 +
x86/has memory protection extensionstrue +
x86/has software guard extensionstrue +