From WikiChip
Difference between revisions of "baikal/baikal-m"
< baikal

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| socket 0 type      =  
 
| socket 0 type      =  
 
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'''Baikal-M''' is an [[octa-core]] {{arch|64}} [[ARM]] system on a chip set to be introduced by [[Baikal Electronics]] in late [[2017]].
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'''Baikal-M''' is an [[octa-core]] {{arch|64}} [[ARM]] system on a chip set to be introduced by [[Baikal Electronics]] in late [[2017]]. This chip, which is fabricated on [[TSMC]]'s [[28 nm process]], operates at 2 GHz and integrates an [[ARM Holdings|ARM]] {{armh|Mali-T628}} MP8 [[IGP]].
  
  
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|max bandwidth=11.92 GiB/s
 
|max bandwidth=11.92 GiB/s
 
|bandwidth schan=11.92 GiB/s
 
|bandwidth schan=11.92 GiB/s
 +
}}
 +
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-T628
 +
| device id          =
 +
| designer            = ARM Holdings
 +
| execution units    = 8
 +
| max displays        =
 +
| max memory          =
 +
| frequency          = ? MHz
 +
 +
| output dsi          = Yes
 +
 +
| max res dsi        = ?
 +
 +
| direct3d ver        = 11
 +
| opencl ver          = 1.1
 +
| opengl ver          = 3.2
 +
| opengl es ver      = 3.1
 +
| openvg ver          = 1.1
 
}}
 
}}
  

Revision as of 21:30, 21 March 2017

Template:mpu Baikal-M is an octa-core 64-bit ARM system on a chip set to be introduced by Baikal Electronics in late 2017. This chip, which is fabricated on TSMC's 28 nm process, operates at 2 GHz and integrates an ARM Mali-T628 MP8 IGP.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
    

L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
     

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-1600
Supports ECCYes
Max Mem8 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-T628
DesignerARM Holdings
Execution Units8
Frequency? MHz
"? MHz" is not a number.
OutputDSI

Max Resolution
DSI?

Standards
Direct3D11
OpenGL3.2
OpenCL1.1
OpenGL ES3.1
OpenVG1.1

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes4
Configsx4
USB
Revision2.0
Rate480 Mib/s
Features8-bit ULPI PHY
UART
Ports2
SATA
Revision3.1
Ports2
I²C
Ports2

Integrated LANYes
GP I/O32 bit
JTAGYes


Networking

[Edit/Modify Network Info]

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Networking
Ethernet
1 GigEYes (Ports: 2)
10GbEYes (Ports: 1)
MII
RGMIIYes (Ports: 2)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Baikal-M - Baikal Electronics#io +
has ecc memory supporttrue +
integrated gpuMali-T628 +
integrated gpu designerARM Holdings +
integrated gpu execution units8 +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
max pcie lanes4 +
supported memory typeDDR4-1600 +