From WikiChip
Difference between revisions of "baikal/baikal-t1"
< baikal

Line 49: Line 49:
 
| socket 0 type      = BGA
 
| socket 0 type      = BGA
 
}}
 
}}
The '''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS32]] [[system on a chip]] introduced by [[Baikal Electronics]] in 2015. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies]] high-performance P5600 cores and is manufactured on [[TSMC]]'s [[28 nm process]]. The Baikal-T1 supports up to 8 GiB of DDR3-1600.
+
'''Baikal-T1''' is a {{arch|32}} [[dual-core]] [[MIPS]] [[system on a chip]] introduced by [[Baikal Electronics]] in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of [[Imagination Technologies]] high-performance P5600 cores and is manufactured on [[TSMC]]'s [[28 nm process]]. The Baikal-T1 supports up to 8 GiB of DDR3-1600.
  
 
The chip consumes less than 5W and can be used in fanless designs.
 
The chip consumes less than 5W and can be used in fanless designs.

Revision as of 12:41, 21 March 2017

Template:mpu Baikal-T1 is a 32-bit dual-core MIPS system on a chip introduced by Baikal Electronics in 2015 for the embedded market. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination Technologies high-performance P5600 cores and is manufactured on TSMC's 28 nm process. The Baikal-T1 supports up to 8 GiB of DDR3-1600.

The chip consumes less than 5W and can be used in fanless designs.

Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associativewrite-back

L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1600
Supports ECCYes
Max Mem8 GiB
Controllers1
Channels1
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 11.92 GiB/s

Expansions

Template:mpu expansions

Networking

The Baikal-T1 has support for 1x10Gb and 2x1Gb Ethernet ports.


Networking
1000Base-T Yes
10GBase-T Yes

Block Diagram

baikal-t1 block diagram.png

has ecc memory supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
supported memory typeDDR3-1600 +