Semiconductor & Computer Engineering
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Difference between revisions of "loongson/godson 2/2h"
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| − | '''Godson-2H''' ('''龙芯2H''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming | + | '''Godson-2H''' ('''龙芯2H''') is a {{arch|64}} [[MIPS]] performance processor developed by [[Institute of Computing Technology of the Chinese Academy of Sciences|ICT]] and later [[Loongson]] for desktop computers. Introduced in late-[[2010]], the Godson-2H operates at up to 1 GHz consuming up to 7 W. This chip was manufactured on [[STMicroelectronics]]' [[65 nm process]]. |
The Godson-2H is actually a complete [[system on a chip]] incorporating the [[northbridge]] along with the [[southbridge]] on-die. Additionally the Godson-2H also incorporates a low-power [[Vivante]] {{vivante|GC800}} [[IGP]] operating at 400 MHz. | The Godson-2H is actually a complete [[system on a chip]] incorporating the [[northbridge]] along with the [[southbridge]] on-die. Additionally the Godson-2H also incorporates a low-power [[Vivante]] {{vivante|GC800}} [[IGP]] operating at 400 MHz. | ||
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| − | | max res vga = | + | | max res vga = 1920x1080 |
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== References == | == References == | ||
* Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012. | * Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012. | ||
| + | * Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper") | ||
Revision as of 13:51, 19 March 2017
Template:mpu Godson-2H (龙芯2H) is a 64-bit MIPS performance processor developed by ICT and later Loongson for desktop computers. Introduced in late-2010, the Godson-2H operates at up to 1 GHz consuming up to 7 W. This chip was manufactured on STMicroelectronics' 65 nm process.
The Godson-2H is actually a complete system on a chip incorporating the northbridge along with the southbridge on-die. Additionally the Godson-2H also incorporates a low-power Vivante GC800 IGP operating at 400 MHz.
In addition to a standalone SoC, the Godson-2H can also operate in slave-mode serving as a cooperative southbridge to the more powerful Godson 3 multi-core processor family.
Cache
- Main article: GS464V § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Graphics
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Integrated Graphics Information
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Expansions
This chip has integrated HyperTransport 1.03 operating at 200, 400, or 800 MHz.
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Expansion Options
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Networking
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Networking
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Die Shot
- 65 nm process
- 152,000,000 transistors
- 117 mm² die size
References
- Xiao, Bin, et al. "Godson-2H: a complex low power SOC in 65nm CMOS." Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on. IEEE, 2012.
- Loongson Technology, "龙芯芯片产品技术白皮书" ("Godson chip product technology white paper")
Facts about "Godson-2H - Loongson"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Godson-2H - Loongson#io + |
| has ecc memory support | true + |
| integrated gpu | GC800 + |
| integrated gpu base frequency | 400 MHz (0.4 GHz, 400,000 KHz) + |
| integrated gpu designer | Vivante + |
| integrated gpu execution units | 4 + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 4-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
| max memory channels | 1 + |
| max pcie lanes | 4 + |
| supported memory type | DDR3-800 + |