From WikiChip
Difference between revisions of "samsung/exynos/3110"
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== Features == | == Features == | ||
− | {{arm features}} | + | {{arm features |
+ | |thumb=No | ||
+ | |thumb2=Yes | ||
+ | |thumbee=No | ||
+ | |vfpv1=No | ||
+ | |vfpv2=No | ||
+ | |vfpv3=Yes | ||
+ | |vfpv3-d16=No | ||
+ | |vfpv3-f16=No | ||
+ | |vfpv4=No | ||
+ | |vfpv4-d16=No | ||
+ | |vfpv5=No | ||
+ | |neon=Yes | ||
+ | }} |
Revision as of 00:21, 1 March 2017
Template:mpu Exynos 3110 is a single-core 32-bit performance ARM system on a chip introduced by Samsung in 2010. The Exynos 3110 was the first model from the Exynos family which found its way into many of Samsung's and Google's devices including the Galaxy S line, Galaxy Tab, and the Nexus S. The Exynos 3110 incorporates a Cortex-A8 core operating at 1 GHz along with a PowerVR SGX540 IGP operating at 200 MHz. This SoC supports up to LPDDR2-200 dual-channel memory.
Cache
- Main article: Cortex-A8 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Graphics
Integrated Graphics Information
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Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Facts about "Exynos 3110 - Samsung"
has ecc memory support | false + |
integrated gpu | PowerVR SGX540 + |
integrated gpu base frequency | 200 MHz (0.2 GHz, 200,000 KHz) + |
integrated gpu designer | Imagination Technologies + |
integrated gpu execution units | 1 + |
integrated gpu max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB) + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
max memory bandwidth | 2.98 GiB/s (3,051.52 MiB/s, 3.2 GB/s, 3,199.751 MB/s, 0.00291 TiB/s, 0.0032 TB/s) + |
max memory channels | 2 + |
supported memory type | LPDDR2-200 + |