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Difference between revisions of "intel/xeon e3/e3-1505m v6"
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'''Xeon E3-1505M v6''' is a {{arch|64}} [[quad-core]] entry-level workstations and dense servers [[x86]] microprocessor introduced by [[Intel]] in [[2017]]. This processor, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is manufactured on Intel's improved [[14 nm process|14nm+ process]]. The E3-1505M v6 operates at 3 GHz with a TDP of 45 W and with a {{intel|Turbo Boost}} frequency of 4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.1 GHz.
 
'''Xeon E3-1505M v6''' is a {{arch|64}} [[quad-core]] entry-level workstations and dense servers [[x86]] microprocessor introduced by [[Intel]] in [[2017]]. This processor, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is manufactured on Intel's improved [[14 nm process|14nm+ process]]. The E3-1505M v6 operates at 3 GHz with a TDP of 45 W and with a {{intel|Turbo Boost}} frequency of 4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2400 memory and incorporates Intel's {{intel|HD Graphics P630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.1 GHz.
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== Cache ==
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{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache size
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|l1 cache=256 KiB
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|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=8-way set associative
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|l1i policy=write-back
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
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|l1d policy=write-back
 +
|l2 cache=1 MiB
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|l2 break=4x256 KiB
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|l2 desc=4-way set associative
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|l2 policy=write-back
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|l3 cache=8 MiB
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|l3 break=4x2 MiB
 +
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 20:12, 8 January 2017

Template:mpu Xeon E3-1505M v6 is a 64-bit quad-core entry-level workstations and dense servers x86 microprocessor introduced by Intel in 2017. This processor, which is based on the Kaby Lake microarchitecture, is manufactured on Intel's improved 14nm+ process. The E3-1505M v6 operates at 3 GHz with a TDP of 45 W and with a Turbo Boost frequency of 4 GHz for a single active core. This MPU supports up to 64 GiB of dual-channel ECC DDR4-2400 memory and incorporates Intel's HD Graphics P630 IGP operating at 350 MHz with a burst frequency of 1.1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB4-way set associativewrite-back
L3$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back
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Facts about "Xeon E3-1505M v6 - Intel"
RDF feed
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description16-way set associative +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +