Difference between revisions of "intel/pentium gold/g4560"

Revision as of 21:46, 5 January 2017

Template:mpu Pentium G4560 is a 64-bit dual-core budget x86 desktop microprocessor introduced by Intel in early 2017. The G4560, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 3.5 GHz with a TDP of 54 W and supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory. Additionally the G4560 incorporates Intel's HD Graphics 610 IGP operating at 350 MHz with a burst frequency of 1.05 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

128 KiB

131,072 B
0.125 MiB

L1I$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	4-way set associative	write-back

L3$

3 MiB

3,072 KiB
3,145,728 B
0.00293 GiB

		2x1.5 MiB		write-back

@@ Line 78: / Line 78: @@
 }}
 '''Pentium G4560''' is a {{arch|64}} [[dual-core]] budget [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2017]]. The G4560, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 3.5 GHz with a TDP of 54 W and supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory. Additionally the G4560 incorporates Intel's {{intel|HD Graphics 610}} [[IGP]] operating at 350 MHz with a burst frequency of 1.05 GHz.
-{{unknown features}}
 == Cache ==
-{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
+{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
-{{cache info
+{{cache size
+|l1 cache=128 KiB
 |l1i cache=64 KiB
 |l1i break=2x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core, write-back)
+|l1i policy=write-back
 |l1d cache=64 KiB
 |l1d break=2x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core, write-back)
+|l1d policy=write-back
 |l2 cache=512 KiB
 |l2 break=2x256 KiB
 |l2 desc=4-way set associative
-|l2 extra=(per core, write-back)
+|l2 policy=write-back
 |l3 cache=3 MiB
 |l3 break=2x1.5 MiB
-|l3 desc=12-way set associative
+|l3 policy=write-back
-|l3 extra=(shared)
 }}

l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +

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Revision as of 21:46, 5 January 2017

Cache