Difference between revisions of "intel/pentium gold/g4620"

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Revision as of 22:46, 5 January 2017

Template:mpu Pentium G4620 is a 64-bit dual-core budget x86 desktop microprocessor introduced by Intel in early 2017. The G4620, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 3.7 GHz with a TDP of 51 W and supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory. Additionally the G4620 incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with a burst frequency of 1.1 GHz.

Cache

Main article: Kaby Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

128 KiB

131,072 B
0.125 MiB

L1I$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back
L1D$	64 KiB 65,536 B 0.0625 MiB	2x32 KiB	8-way set associative	write-back

L2$

512 KiB

0.5 MiB
524,288 B
4.882812e-4 GiB

		2x256 KiB	4-way set associative	write-back

L3$

3 MiB

3,072 KiB
3,145,728 B
0.00293 GiB

		2x1.5 MiB		write-back

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/pentium_gold/g4620&oldid=32940"

Facts about "Pentium Gold G4620 - Intel"

RDF feed

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Pentium Gold G4620 - Intel#package + and Pentium Gold G4620 - Intel#io +
base frequency	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Sunrise Point + and Union Point +
clock multiplier	37 +
core count	2 +
core family	6 +
core model	158 +
core name	Kaby Lake S +
core stepping	S0 +
core voltage (max)	1.52 V (15.2 dV, 152 cV, 1,520 mV) +
core voltage (min)	0.25 V (2.5 dV, 25 cV, 250 mV) +
cpuid	0x306A9 +
designer	Intel +
device id	0x5912 +
family	Pentium + and Pentium Gold +
first announced	January 3, 2017 +
first launched	January 3, 2017 +
full page name	intel/pentium gold/g4620 +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel supervisor mode execution protection	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
integrated gpu	HD Graphics 630 +
integrated gpu base frequency	350 MHz (0.35 GHz, 350,000 KHz) +
integrated gpu designer	Intel +
integrated gpu execution units	24 +
integrated gpu max frequency	1,100 MHz (1.1 GHz, 1,100,000 KHz) +
integrated gpu max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) +
isa	x86-64 +
isa family	x86 +
l1$ size	128 KiB (131,072 B, 0.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	64 KiB (65,536 B, 0.0625 MiB) +
l2$ description	4-way set associative +
l2$ size	0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size	3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
ldate	January 3, 2017 +
manufacturer	Intel +
market segment	Desktop +
max cpu count	1 +
max junction temperature	373.15 K (100 °C, 212 °F, 671.67 °R) +
max memory	65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth	35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels	2 +
max pcie lanes	16 +
max storage temperature	398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitecture	Kaby Lake +
min junction temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature	248.15 K (-25 °C, -13 °F, 446.67 °R) +
model number	G4620 +
name	Pentium Gold G4620 +
package	FCLGA-1151 +
part number	BX80677G4620 +
platform	Kaby Lake +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 93.00 (€ 83.70, £ 75.33, ¥ 9,609.69) +
s-spec	SR35E +
series	G4600 +
smp max ways	1 +
socket	LGA-1151 +
supported memory type	DDR3L-1600 + and DDR4-2400 +
tdp	51 W (51,000 mW, 0.0684 hp, 0.051 kW) +
technology	CMOS +
thread count	4 +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +
x86/has software guard extensions	true +

@@ Line 78: / Line 78: @@
 }}
 '''Pentium G4620''' is a {{arch|64}} [[dual-core]] budget [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2017]]. The G4620, which is based on the {{intel|Kaby Lake|l=arch}} microarchitecture, is fabricated on Intel's improved [[14 nm|14nm+ process]]. This processor operates at 3.7 GHz with a TDP of 51 W and supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory. Additionally the G4620 incorporates Intel's {{intel|HD Graphics 630}} [[IGP]] operating at 350 MHz with a burst frequency of 1.1 GHz.
-{{unknown features}}
 == Cache ==
-{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
+{{main|intel/microarchitectures/kaby_lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
-{{cache info
+{{cache size
+|l1 cache=128 KiB
 |l1i cache=64 KiB
 |l1i break=2x32 KiB
 |l1i desc=8-way set associative
-|l1i extra=(per core, write-back)
+|l1i policy=write-back
 |l1d cache=64 KiB
 |l1d break=2x32 KiB
 |l1d desc=8-way set associative
-|l1d extra=(per core, write-back)
+|l1d policy=write-back
 |l2 cache=512 KiB
 |l2 break=2x256 KiB
 |l2 desc=4-way set associative
-|l2 extra=(per core, write-back)
+|l2 policy=write-back
 |l3 cache=3 MiB
 |l3 break=2x1.5 MiB
-|l3 desc=12-way set associative
+|l3 policy=write-back
-|l3 extra=(shared)
 }}

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Revision as of 22:46, 5 January 2017

Cache