Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/celeron/g3950"
(+graphics) |
|||
| Line 124: | Line 124: | ||
| device id = 0x5902 | | device id = 0x5902 | ||
| designer = Intel | | designer = Intel | ||
| − | | execution units = | + | | execution units = 12 |
| max displays = 3 | | max displays = 3 | ||
| max memory = 64 GiB | | max memory = 64 GiB | ||
Revision as of 16:54, 5 January 2017
Template:mpu Celeron G3950 is a 64-bit dual-core budget x86 desktop microprocessors introduced by Intel in early 2017. The G3950, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14nm+ process. This processor operates at 3 GHz and with a TDP of 51 W and supports up to 64 GiB of dual-channel non-ECC DDR4-2400. Additionally the G3950 incorporates Intel's HD Graphics 610 IGP operating at 350 MHz with a burst frequency of 1.05 GHz.
Cache
- Main article: Kaby Lake § Cache
 |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
|||||||||||||||||||||||||||||||||||||
Memory controller
 |
Integrated Memory Controller
|
|||||||||||||
|
||||||||||||||
Expansions
 |
Expansion Options
|
|||||||
|
||||||||
Graphics
 |
Integrated Graphics Information
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
Facts about "Celeron G3950 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron G3950 - Intel#io + |
| device id | 0x5902 + |
| has ecc memory support | false + |
| integrated gpu | HD Graphics 610 + |
| integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
| integrated gpu designer | Intel + |
| integrated gpu execution units | 12 + |
| integrated gpu max frequency | 1,050 MHz (1.05 GHz, 1,050,000 KHz) + |
| integrated gpu max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB) + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 12-way set associative + |
| l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
| max memory bandwidth | 35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2400 + |