Semiconductor & Computer Engineering
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Difference between revisions of "intel/core i3/i3-7101te"
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|bandwidth schan=15.89 GiB/s | |bandwidth schan=15.89 GiB/s | ||
|bandwidth dchan=31.79 GiB/s | |bandwidth dchan=31.79 GiB/s | ||
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| + | == Expansions == | ||
| + | {{expansions | ||
| + | | pcie revision = 3.0 | ||
| + | | pcie lanes = 16 | ||
| + | | pcie config = 1x16 | ||
| + | | pcie config 2 = 2x8 | ||
| + | | pcie config 3 = 1x8+2x4 | ||
}} | }} | ||
Revision as of 19:11, 4 January 2017
Template:mpu Core i3-7101TE is a 64-bit dual-core low-end performance x86 microprocessor introduced by Intel in early 2017 for the desktop and embedded market. This chip, which is based on the Kaby Lake microarchitecture, is fabricated on Intel's improved 14 nm+ process. This processor, which has a base frequency of 3.4 GHz with a TDP of 35 Watts, supports up to 64 GiB of dual-channel DDR4-2133. The i3-7101TE incorporates Intel's HD Graphics 630 IGP operating at 350 MHz with burst frequency of 1.1 GHz.
Cache
- Main article: Kaby Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Facts about "Core i3-7101TE - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Core i3-7101TE - Intel#io + |
| has ecc memory support | true + |
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
| max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
| max memory channels | 2 + |
| max pcie lanes | 16 + |
| supported memory type | DDR3L-1600 + and DDR4-2133 + |