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'''CN5745-600 SSP''' is a {{arch|64}} [[deca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.
 
'''CN5745-600 SSP''' is a {{arch|64}} [[deca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates ten {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration.
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== Cache ==
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{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
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{{cache size
 +
|l1 cache=480 KiB
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|l1i cache=320 KiB
 +
|l1i break=10x32 KiB
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|l1d cache=160 KiB
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|l1d break=10x16 KiB
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|l2 cache=2 MiB
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|l2 break=1x2 MiB
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}}
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== Memory controller ==
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{{memory controller
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|type=DDR2-800
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|ecc=Yes
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|max mem=
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|controllers=1
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|channels=2
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|width=64 bit
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|max bandwidth=11.92 GiB/s
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|bandwidth schan=5.96 GiB/s
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|bandwidth dchan=11.92 GiB/s
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}}
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== Expansions ==
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{{expansions
 +
|pcie revision=1.0
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|pcie lanes=8
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|pcie config=x4
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|pcie config 2=x8
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|uart=yes
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|gp io=Yes
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}}
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== Networking ==
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Interface options:
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* 8-lanes [[PCIe]] + 8-lanes PCIe
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* 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
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* 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
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{{network
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|mii opts=Yes
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|sgmii=yes
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|sgmii ports=4
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|xaui=1
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|xaui ports=1
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}}
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== Hardware Accelerators ==
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{{accelerators
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|encryption=Yes
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|encryption type=3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
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|compression=Yes
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|decompression=Yes
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|tcp=Yes
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|qos=Yes
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|raid=Yes
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|raid5=Yes
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|raid6=Yes
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}}
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== Block diagram ==
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[[File:cn57xx block diagram.png|750px]]
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== Datasheet ==
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* [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]]

Revision as of 13:29, 29 December 2016

Template:mpu CN5745-600 SSP is a 64-bit deca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates ten cnMIPS cores, operates at 600 MHZ and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$480 KiB
491,520 B
0.469 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB  
L1D$160 KiB
163,840 B
0.156 MiB
10x16 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART
GP I/OYes


Networking

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
Types3DES, AES-GCM, AES up to 256-bit, SHA-1, SHA-2 up to SHA-512, RSA up to 8192, DH
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram

cn57xx block diagram.png

Datasheet

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Facts about "CN5745-600 SSP - Cavium"
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CN5745-600 SSP - Cavium#package + and CN5745-600 SSP - Cavium#io +
base frequency600 MHz (0.6 GHz, 600,000 kHz) +
core count10 +
designerCavium +
familyOCTEON Plus +
first announcedJune 26, 2007 +
first launchedAugust 2007 +
full page namecavium/octeon plus/cn5745-600bg1217-ssp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size480 KiB (491,520 B, 0.469 MiB) +
l1d$ size160 KiB (163,840 B, 0.156 MiB) +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateAugust 2007 +
main imageFile:Octeon CN57xx.svg +
manufacturerTSMC +
market segmentStorage +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
microarchitecturecnMIPS +
model numberCN5745-600 SSP +
nameCavium CN5745-600 SSP +
packageFCBGA-1217 +
part numberCN5745-600BG1217-SSP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN57xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count10 +
word size64 bit (8 octets, 16 nibbles) +