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Difference between revisions of "cavium/octeon plus/cn5750-1000bg1217-ssp"
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| package 0 pins = 1217 | | package 0 pins = 1217 | ||
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| − | | package 0 width = | + | | package 0 width = 40 mm |
| − | | package 0 length = | + | | package 0 length = 40 mm |
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| socket 0 = BGA-1217 | | socket 0 = BGA-1217 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
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| + | '''CN5750-1000 SSP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] secure storage processor (SSP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], encryption, networking, TCP & [[QoS]] acceleration. | ||
Revision as of 00:38, 29 December 2016
Template:mpu CN5750-1000 SSP is a 64-bit dodeca-core MIPS secure storage processor (SSP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, encryption, networking, TCP & QoS acceleration.
Facts about "CN5750-1000 SSP - Cavium"
