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| '''CN5860-1000 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration. | '''CN5860-1000 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure communication microprocessor (SCP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration. | ||
Revision as of 22:51, 22 June 2017
Template:mpu CN5860-1000 SCP is a 64-bit hexadeca-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2007. This processor, which incorporates sixteen cnMIPS cores, operates at 1 GHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of secure communication software such as encryption, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
|  | Cache Organization  Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. | ||||||||||||||||||||||||
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Memory controller
|  | Integrated Memory Controller | |||||||||||||
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Expansions
|  | Expansion Options | |||||||||||||||
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Networking
|  | Networking | |||||||
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Hardware Accelerators
[Edit/Modify Accelerators Info]
|  | Hardware Accelerators | |||||||||||
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Block diagram
Datasheet
Facts about "CN5860-1000 SCP  - Cavium"
| has ecc memory support | true + | 
| has hardware accelerators for cryptography | true + | 
| has hardware accelerators for network quality of service processing | true + | 
| has hardware accelerators for tcp packet processing | true + | 
| l1$ size | 768 KiB (786,432 B, 0.75 MiB) + | 
| l1d$ description | 64-way set associative + | 
| l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + | 
| l1i$ description | 64-way set associative + | 
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + | 
| l2$ description | 8-way set associative + | 
| l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + | 
| max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + | 
| max memory channels | 1 + | 
| supported memory type | DDR2-800 + | 
