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'''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in mid-[[2005]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units.
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'''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in [[2007]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units.

Revision as of 02:27, 11 December 2016

Cavium OCTEON Plus
Developer Cavium
Manufacturer TSMC
Type System on chips
Introduction October 9, 2006 (announced)
February, 2007 (launch)
Architecture MIPS64 R2 network SoCs
ISA MIPS64
µarch cnMIPS
Word size 64 bit
8 octets
16 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 600 MHz-1,000 MHz
Package FCBGA-1521
Socket BGA-1521
Succession
OCTEON OCTEON II

OCTEON Plus was a family of 64-bit multi-core MIPS microprocessors designed by Cavium and introduced in 2007. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the OCTEON family offering double the cache, double the clock speeds, and double the number of various acceleration units.

Facts about "OCTEON Plus - Cavium"
designerCavium +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus +
instance ofsystem on a chip family +
instruction set architectureMIPS64 +
main designerCavium +
manufacturerTSMC +
microarchitecturecnMIPS +
nameCavium OCTEON Plus +
packageFCBGA-1521 +
process130 nm (0.13 μm, 1.3e-4 mm) +
socketBGA-1521 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +