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Difference between revisions of "cavium/octeon/cn3830-500bg1521-nsp"
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The '''CN3830-500 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | The '''CN3830-500 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=160 KiB | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=64-way set associative | ||
+ | |l1d cache=32 KiB | ||
+ | |l1d break=4x8 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l1d policy=Write-through | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=1x1 MiB | ||
+ | |l2 desc=8-way set associative | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-800 | ||
+ | |ecc=Yes | ||
+ | |max mem=16 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=128 bit | ||
+ | |max bandwidth=11.92 GiB/s | ||
+ | |bandwidth schan=11.92 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=64 bit | ||
+ | |pcix clock=133.33 MHz | ||
+ | |pcix rate=1,017.25 MiB/s | ||
+ | |pcix extra=host or slave | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=8 | ||
+ | |spi opts=Yes | ||
+ | |spi42=Yes | ||
+ | |spi42 ports=2 | ||
+ | }} | ||
+ | |||
+ | == Hardware Accelerators == | ||
+ | {{accelerators | ||
+ | |encryption=Yes | ||
+ | |encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | |regex=Yes | ||
+ | |regex feature=16 Engines | ||
+ | |compression=Yes | ||
+ | |decompression=Yes | ||
+ | |tcp=Yes | ||
+ | |qos=Yes | ||
+ | }} |
Revision as of 22:22, 10 December 2016
Template:mpu The CN3830-500 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
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Facts about "CN3830-500 NSP - Cavium"