From WikiChip
Difference between revisions of "cavium/octeon/cn3840-500bg1521-exp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3840-500 EXP}} {{mpu | name = Cavium CN3840-500 EXP | no image = | image = octeon cn38xx.png | image size =...")
 
Line 89: Line 89:
 
| socket 0 type      =  
 
| socket 0 type      =  
 
}}
 
}}
 +
The '''CN3840-500 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Revision as of 19:31, 10 December 2016

Template:mpu The CN3840-500 EXP is a 64-bit octa-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3840-500bg1521-exp&oldid=31420"
Facts about "CN3840-500 EXP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3840-500 EXP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count8 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedAugust 22, 2005 +
first launchedAugust 22, 2005 +
full page namecavium/octeon/cn3840-500bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size320 KiB (327,680 B, 0.313 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateAugust 22, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3840-500 EXP +
nameCavium CN3840-500 EXP +
packageFCBGA-1521 +
part numberCN3840-500BG1521-EXP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +