Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3005-300bg350-cp"
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Revision as of 16:49, 10 December 2016
Template:mpu The CN3005-300 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 memory.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Hardware Accelerators
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram
Datasheet
Facts about "CN3005-300 CP - Cavium"
| base frequency | 300 MHz (0.3 GHz, 300,000 kHz) + |
| core count | 1 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | January 30, 2006 + |
| first launched | May 1, 2006 + |
| full page name | cavium/octeon/cn3005-300bg350-cp + |
| has ecc memory support | false + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 2-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l2$ description | 2-way set associative + |
| l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
| ldate | May 1, 2006 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
| max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3005-300 CP + |
| name | Cavium CN3005-300 CP + |
| part number | CN3005-300BG350-CP + |
| power dissipation | 2 W (2,000 mW, 0.00268 hp, 0.002 kW) + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| release price | $ 19.00 (€ 17.10, £ 15.39, ¥ 1,963.27) + |
| series | CN3000 + |
| smp max ways | 1 + |
| supported memory type | DDR2-533 + |
| technology | CMOS + |
| thread count | 1 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
