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Difference between revisions of "cavium/octeon/cn3120-500bg868-cp"
< cavium‎ | octeon

(→‎Cache)
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|l2 break=1x256 KiB
 
|l2 break=1x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-667
 +
|ecc=Yes
 +
|max mem=4 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=64 bit
 +
|max bandwidth=4.97 GiB/s
 +
|bandwidth schan=4.97 GiB/s
 +
}}
 +
 +
Optional low-latency controller for content-based processing and meta data
 +
 +
{{memory controller
 +
|type=DDR2-667
 +
|ecc=Yes
 +
|max mem=2 GiB
 +
|controllers=1
 +
|channels=1
 +
|width=16 bit
 +
|max bandwidth=1.24 GiB/s
 +
|bandwidth schan=1.24 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|pcix width=32 bit
 +
|pcix clock=100 MHz
 +
|pcix rate=381.5 MiB/s
 +
|pci extra=host or slave
 +
|usb revision=2.0
 +
|usb ports=1
 +
|usb rate=60 MB/s
 +
|usb extra=host / PHY
 +
|uart=yes
 +
|uart ports=2
 +
|gp io=Yes
 +
}}
 +
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=3
 +
|gmii=yes
 +
|gmii ports=1
 +
|pcm=Yes
 
}}
 
}}

Revision as of 14:22, 9 December 2016

Template:mpu The CN3120-500 SCP is a 64-bit dual-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 500 MHz. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2
GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3120-500bg868-cp&oldid=30976"
Facts about "CN3120-500 CP - Cavium"
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CN3120-500 CP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count2 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3120-500bg868-cp +
has ecc memory supporttrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3120-500 CP +
nameCavium CN3120-500 CP +
packageHSBGA-868 +
part numberCN3120-500BG868-CP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +