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Difference between revisions of "cavium/octeon/cn3120-550bg868-cp"
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| + | The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | ||
Revision as of 03:39, 9 December 2016
Template:mpu The CN3120-550 SCP is a 64-bit dual-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing such as high-performance I/O packet processing, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Facts about "CN3120-550 CP - Cavium"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | CN3120-550 CP - Cavium#package + |
| base frequency | 550 MHz (0.55 GHz, 550,000 kHz) + |
| core count | 2 + |
| core name | cnMIPS + |
| designer | Cavium + |
| family | OCTEON + |
| first announced | January 30, 2006 + |
| first launched | May 1, 2006 + |
| full page name | cavium/octeon/cn3120-550bg868-cp + |
| has ecc memory support | true + |
| has hardware accelerators for network quality of service processing | true + |
| has hardware accelerators for tcp packet processing | true + |
| instance of | microprocessor + |
| isa | MIPS64 + |
| isa family | MIPS + |
| l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
| l1d$ description | 64-way set associative + |
| l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
| ldate | May 1, 2006 + |
| main image |  + |
| manufacturer | TSMC + |
| market segment | Embedded + |
| max cpu count | 1 + |
| max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
| max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
| max memory channels | 1 + |
| microarchitecture | cnMIPS + |
| model number | CN3120-550 CP + |
| name | Cavium CN3120-550 CP + |
| package | HSBGA-868 + |
| part number | CN3120-550BG868-CP + |
| power dissipation | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
| release price | $ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) + |
| series | CN3100 + |
| smp max ways | 1 + |
| supported memory type | DDR2-667 + |
| technology | CMOS + |
| thread count | 2 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
