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Difference between revisions of "cavium/octeon/cn3110-500bg868-nsp"
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The '''CN3110-500 NSP''' is a {{arch|64}} [[single-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Revision as of 01:37, 9 December 2016

Template:mpu The CN3110-500 NSP is a 64-bit single-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

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Facts about "CN3110-500 NSP - Cavium"
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CN3110-500 NSP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3110-500bg868-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size40 KiB (40,960 B, 0.0391 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3110-500 NSP +
nameCavium CN3110-500 NSP +
packageHSBGA-868 +
part numberCN3110-500BG868-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +