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Difference between revisions of "cavium/octeon/cn3010-500bg525-cp"
< cavium‎ | octeon

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|channels=1
 
|channels=1
 
|width=32 bit
 
|width=32 bit
|max bandwidth=1.986 MiB/s
+
|max bandwidth=1.986 GiB/s
|bandwidth schan=1.986 MiB/s
+
|bandwidth schan=1.986 GiB/s
 
}}
 
}}
  
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|gp io=Yes
 
|gp io=Yes
 
}}
 
}}
 +
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=3
 +
|pcm=yes
 +
}}
 +
 +
== Features ==
 +
Hardware acceleration units:
 +
* Packet I/O processing
 +
* QoS
 +
* TCP Acceleration
 +
 +
== Block diagram ==
 +
[[File:cn3010 block diagram.png|750px]]
 +
 +
== Datasheet ==
 +
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]

Revision as of 20:44, 8 December 2016

Template:mpu The CN3010-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3005 equivalent, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$24 KiB
24,576 B
0.0234 MiB
L1I$16 KiB
16,384 B
0.0156 MiB
1x16 KiB2-way set associative 
L1D$8 KiB
8,192 B
0.00781 MiB
1x8 KiB64-way set associativeWrite-through

L2$128 KiB
0.125 MiB
131,072 B
1.220703e-4 GiB
  1x128 KiB4-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-533
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width32 bit
Max Bandwidth1.986 GiB/s
2,033.664 MiB/s
2.132 GB/s
2,132.451 MB/s
0.00194 TiB/s
0.00213 TB/s
Bandwidth
Single 1.986 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI
Width32 bit
Clock66.66 MHz
Rate254.31 MiB/s
Featureshost or slave
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2

GP I/OYes


Networking

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
RGMIIYes (Ports: 3)
TDM/PCMYes

Features

Hardware acceleration units:

  • Packet I/O processing
  • QoS
  • TCP Acceleration

Block diagram

cn3010 block diagram.png

Datasheet

has ecc memory supporttrue +
l1$ size24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
max memory bandwidth1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) +
max memory channels1 +
supported memory typeDDR2-533 +