Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon/cn3010-300bg525-cp"
(Created page with "{{cavium title|CN3010-300 CP}} {{mpu | name = Cavium CN3010-300 CP | no image = | image = cn3005-15.png | image size = | cap...") |
|||
| Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| + | The '''CN3010-300 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-300bg350-cp|CN3015 equivalent}} as well as support for TDM/PCM (VoIP support). | ||
Revision as of 19:19, 8 December 2016
Template:mpu The CN3010-300 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the CN3015 equivalent as well as support for TDM/PCM (VoIP support).