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Difference between revisions of "socionext/sc2a11"
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'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
 
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
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== Cache ==
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{{main|arm holdings/microarchitectures/cortex-a53#Memory_Hierarchy|l1=Cortex-A53 § Cache}}
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{{cache size
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|l1 cache = 1.5 MiB
 +
|l1i cache=768 KiB
 +
|l1i break=24x32 KiB
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|l1i desc=2-way set associative
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|l1d cache=768 KiB
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|l1d break=24x32 KiB
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|l1d desc=4-way set associative
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|l2 cache=1.5 MiB
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|l2 break=2x256 KiB
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|l2 desc=16-way set associative
 +
|l3 cache=4 MiB
 +
}}

Revision as of 02:34, 4 December 2016

Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB2-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB4-way set associative 
L2$1.5 MiB
1,536 KiB
1,572,864 B
0.00146 GiB
  2x256 KiB16-way set associative 
L3$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
     
Retrieved from "https://en.wikichip.org/w/index.php?title=socionext/sc2a11&oldid=30353"
Facts about "SC2A11 - Socionext"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
SC2A11 - Socionext#io +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus typeAMBA +
core count24 +
core nameCortex-A53 +
designerSocionext + and ARM Holdings +
first announcedNovember 14, 2016 +
first launched2017 +
full page namesocionext/sc2a11 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description4-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description2-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate3000 +
main imageFile:SC2A11 IMG01.jpg +
market segmentServer +, Networking + and IoT +
max cpu count64 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes4 +
microarchitectureCortex-A53 +
model numberSC2A11 +
nameSocionext SC2A11 +
smp max ways64 +
supported memory typeDDR4-2133 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technologyCMOS +
thread count24 +
word size64 bit (8 octets, 16 nibbles) +