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(Created page with "{{socionext title|SC2A11}} '''SC2A11''' is a {{arch|64}} tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge com...")
 
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{{socionext title|SC2A11}}
 
{{socionext title|SC2A11}}
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{{mpu
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| name                = Socionext SC2A11
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| no image            = Yes
 +
| image              =
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| image size          =
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| caption            =
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| designer            = Socionext
 +
| designer 2          = ARM Holdings
 +
| manufacturer        =
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| model number        = SC2A11
 +
| part number        =
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| part number 1      =
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| part number 2      =
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| part number 3      =
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| market              = Server
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| market 2            = Networking
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| market 3            = IoT
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| first announced    = November 14, 2016
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| first launched      =
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| last order          =
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| last shipment      =
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| release price      =
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| family              =
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| series              =
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| locked              =
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| frequency          = 1,000 MHz
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| bus type            = AMBA
 +
| bus speed          = <!-- (Property::bus speed) -->
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| bus rate            = <!-- (Property::bus rate) -->
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| bus links          = <!-- ?x bus rate -->
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| clock multiplier    =
 +
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| isa family          = ARM
 +
| isa                = ARMv8
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| microarch          = Cortex-A53
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| platform            =
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| chipset            =
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| core name          =
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| core family        = Cortex-A53
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| core model          =
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| core stepping      =
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| transistors        =
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| technology          = CMOS
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| die area            = <!-- XX mm² -->
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| die width          =
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| die length          =
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| word size          = 64 bit
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| core count          = 24
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| thread count        = 24
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| max cpus            =
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| max memory          =
 +
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| electrical          = <!-- put Yes if electrical info is added -->
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| power              = <!-- power consumption  -->
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| v core              =
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| v core tolerance    =
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| v io                =
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| v io tolerance      =
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| v io 2              = <!-- OR ... -->
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| v io 3              =
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| sdp                =
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| tdp                =
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| tdp typical        =
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| ctdp down          =
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| ctdp down frequency =
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| ctdp up            =
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| ctdp up frequency  =
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| temp min            = <!-- use TJ/TC whenever possible instead -->
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| temp max            =
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| tjunc min          = <!-- .. °C -->
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| tjunc max          =
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| tcase min          =
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| tcase max          =
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| tstorage min        =
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| tstorage max        =
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| tambient min        =
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| tambient max        =
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| package module 1    =
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| package module 2    =
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| packaging          = <!-- put Yes if packaging info is added -->
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| package 0          =
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| package 0 type      =
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| package 0 pins      =
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| package 0 pitch    =
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| package 0 width    =
 +
| package 0 length    =
 +
| package 0 height    =
 +
| socket 0            =
 +
| socket 0 type      =
 +
}}
 
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.
 
'''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Revision as of 03:19, 4 December 2016

Template:mpu SC2A11 is a 64-bit tetracosa-core ARM system on a chip designed by Socionext for low-power servers and cloud/IoT edge computing. This chip, which incorporates 24 ultra-low power Cortex-A53 cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory.

Retrieved from "https://en.wikichip.org/w/index.php?title=socionext/sc2a11&oldid=30349"
Facts about "SC2A11 - Socionext"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
SC2A11 - Socionext#io +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus typeAMBA +
core count24 +
core nameCortex-A53 +
designerSocionext + and ARM Holdings +
first announcedNovember 14, 2016 +
first launched2017 +
full page namesocionext/sc2a11 +
has ecc memory supporttrue +
instance ofmicroprocessor +
isaARMv8 +
isa familyARM +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description4-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description2-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldate3000 +
main imageFile:SC2A11 IMG01.jpg +
market segmentServer +, Networking + and IoT +
max cpu count64 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
max pcie lanes4 +
microarchitectureCortex-A53 +
model numberSC2A11 +
nameSocionext SC2A11 +
smp max ways64 +
supported memory typeDDR4-2133 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
technologyCMOS +
thread count24 +
word size64 bit (8 octets, 16 nibbles) +