From WikiChip
Difference between revisions of "mediatek/helio/mt6795m"
< mediatek‎ | helio

Line 129: Line 129:
 
| opencl es ver      = 3.1
 
| opencl es ver      = 3.1
 
| vulkan ver          = 1.0
 
| vulkan ver          = 1.0
 +
}}
 +
 +
== Wireless ==
 +
{{wireless links
 +
| 2g                = Yes
 +
| csd              = Yes
 +
| gsm              =
 +
| gprs              = Yes
 +
| edge              =
 +
| cdmaone          =
 +
| is-95a            =
 +
| is-95b            =
 +
| 3g                = Yes
 +
| cdma2000          =
 +
| cdma2000 1x      =
 +
| cdma2000 1xev-do  =
 +
| cdma2000 1x adv  =
 +
| umts              = Yes
 +
| wcdma            = 
 +
| td-scdma          = Yes
 +
| dc-hsdpa          = Yes
 +
| hsdpa            =
 +
| hsupa            = Yes
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          = Yes
 +
| ue cat            = 4
 
}}
 
}}

Revision as of 03:45, 3 December 2016

Template:mpu Helio X10 (MT6795M) is a 64-bit octa-core ARM LTE system on a chip designed by MediaTek and introduced in early-2014. This SoC, which incorporates eight Cortex-A53 cores and is manufactured on TSMC's 28 nm process, operates at up to 2 GHz and supports dual-channel LPDDR3-933. This chip incorporates the PowerVR G6200 IGP operating at 550 MHz. This SoC has a modem supporting LTE User Equipment (UE) category 4.

This SoC is made of 2 clusters of 4-core each (Cortex-A53) linked together via a CCI-400, a NEON engine, and Cortex-R4 core for the second MCU subsystem.

Cache

Main article: Cortex-A53 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB4-way set associative 

L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-933
Supports ECCNo
Max Mem4 GiB
Controllers1
Channels2
Max Bandwidth13.9 GiB/s
14,233.6 MiB/s
14.925 GB/s
14,925.011 MB/s
0.0136 TiB/s
0.0149 TB/s
Bandwidth
Single 6.95 GiB/s
Double 13.9 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUPowerVR G6200
DesignerImagination Technologies
Frequency550 MHz
0.55 GHz
550,000 KHz

Standards
Direct3D10.0
OpenGL3.2
OpenCL1.2
Vulkan1.0

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
2G
CSD Yes
GPRS Yes
3G
UMTS
TD-SCDMAYes
DC-HSDPAYes
HSUPAYes
4G
LTE Advanced
E-UTRANYes
UE Cat4
has 2g supporttrue +
has 3g supporttrue +
has 4g supporttrue +
has csd supporttrue +
has dc-hsdpa supporttrue +
has e-utran supporttrue +
has ecc memory supportfalse +
has gprs supporttrue +
has hsupa supporttrue +
has lte advanced supporttrue +
has td-scdma supporttrue +
has umts supporttrue +
integrated gpuPowerVR G6200 +
integrated gpu base frequency550 MHz (0.55 GHz, 550,000 KHz) +
integrated gpu designerImagination Technologies +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth13.9 GiB/s (14,233.6 MiB/s, 14.925 GB/s, 14,925.011 MB/s, 0.0136 TiB/s, 0.0149 TB/s) +
max memory channels2 +
supported memory typeDDR3-933 +
user equipment category4 +