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Difference between revisions of "intel/xeon e7/e7-2803"
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'''Xeon E7-2803''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. | '''Xeon E7-2803''' is a {{arch|64}} hexa-core [[x86]] data center microprocessor that supports up to 2 sockets. This first generation ({{intel|Westmere|Westmere}}-based) {{intel|Xeon E7}} processor operates at 1.73 GHz with a TDP of 105 W but does not support {{intel|turbo boost technology}}. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory. | ||
Revision as of 03:40, 2 December 2016
Template:mpu Xeon E7-2803 is a 64-bit hexa-core x86 data center microprocessor that supports up to 2 sockets. This first generation (Westmere-based) Xeon E7 processor operates at 1.73 GHz with a TDP of 105 W but does not support turbo boost technology. This processor supports up to 4 channels of DDR3, supporting up to 1 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
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Integrated Memory Controller
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Features
[Edit/Modify Supported Features]
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Supported x86 Extensions & Processor Features
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Facts about "Xeon E7-2803 - Intel"
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d + and Extended Page Tables + |
| has intel enhanced speedstep technology | true + |
| has intel trusted execution technology | true + |
| has intel vt-d technology | true + |
| has intel vt-x technology | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) + |
| max memory bandwidth | 23.84 GiB/s (24,412.16 MiB/s, 25.598 GB/s, 25,598.005 MB/s, 0.0233 TiB/s, 0.0256 TB/s) + |
| max memory channels | 4 + |
| supported memory type | DDR3-800 + |