Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e7/e7-2850"
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== Cache == | == Cache == | ||
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | {{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}} | ||
| − | {{cache | + | {{cache size |
| + | |l1 cache = 640 KiB | ||
|l1i cache=320 KiB | |l1i cache=320 KiB | ||
|l1i break=10x32 KiB | |l1i break=10x32 KiB | ||
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
| − | |l1i | + | |l1i policy=write-back |
|l1d cache=320 KiB | |l1d cache=320 KiB | ||
|l1d break=10x32 KiB | |l1d break=10x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
| − | |l1d | + | |l1d policy=write-back |
|l2 cache=2.56 MiB | |l2 cache=2.56 MiB | ||
|l2 break=10x256 KiB | |l2 break=10x256 KiB | ||
|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
| − | |l2 | + | |l2 policy=write-back |
|l3 cache=24 MiB | |l3 cache=24 MiB | ||
| + | |l3 break=10x2.4 MiB | ||
|l3 desc=16-way set associative | |l3 desc=16-way set associative | ||
| + | |l3 policy=write-back | ||
}} | }} | ||
Revision as of 00:38, 2 December 2016
Template:mpu Xeon E7-2850 is a 64-bit deca-core x86 data center microprocessor that supports up to 2 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2 GHz with turob frequency of 2.4 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 1 TB of memory.
Contents
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3-800, DDR3-978, DDR3-1066 |
| Controllers | 1 |
| Channels | 4 |
| ECC Support | Yes |
| Max memory | 1024 GB |
Features
Facts about "Xeon E7-2850 - Intel"
| l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |