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Difference between revisions of "intel/xeon e7/e7-4860"
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(Cache)
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== Cache ==
 
== Cache ==
 
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
 
{{main|intel/microarchitectures/westmere#Memory_Hierarchy|l1=Westmere § Cache}}
{{cache info
+
{{cache size
 +
|l1 cache = 640 KiB
 
|l1i cache=320 KiB
 
|l1i cache=320 KiB
 
|l1i break=10x32 KiB
 
|l1i break=10x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
|l1i extra=(per core)
+
|l1i policy=write-back
 
|l1d cache=320 KiB
 
|l1d cache=320 KiB
 
|l1d break=10x32 KiB
 
|l1d break=10x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
|l1d extra=(per core)
+
|l1d policy=write-back
 
|l2 cache=2.56 MiB
 
|l2 cache=2.56 MiB
 
|l2 break=10x256 KiB
 
|l2 break=10x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
|l2 extra=(per core)
+
|l2 policy=write-back
 
|l3 cache=24 MiB
 
|l3 cache=24 MiB
 +
|l3 break=10x2.4 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 +
|l3 policy=write-back
 
}}
 
}}
  

Revision as of 00:35, 2 December 2016

Template:mpu Xeon E7-4860 is a 64-bit deca-core x86 data center microprocessor that supports up to 4 sockets. This first generation Xeon E7 processor, Westmere-based, operates at a base frequency of 2.26 GHz with turob frequency of 2.66 GHz for 2 active cores. This chip has a TDP of 130 W, supporting up to 4 channels of DDR3 with support of up to 2 TB of memory.

Cache

Main article: Westmere § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB4-way set associativewrite-back
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back

L2$2.56 MiB
2,621.44 KiB
2,684,354.56 B
0.0025 GiB
  10x256 KiB8-way set associativewrite-back

L3$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  10x2.4 MiB16-way set associativewrite-back

Graphics

This SoC has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR3-800, DDR3-978, DDR3-1066
Controllers 1
Channels 4
ECC Support Yes
Max memory 2048 GB

Features

Template:mpu features

Facts about "Xeon E7-4860 - Intel"
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description4-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.56 MiB (2,621.44 KiB, 2,684,354.56 B, 0.0025 GiB) +
l3$ description16-way set associative +
l3$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +