From WikiChip
Difference between revisions of "intel/celeron/p4600"
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|l3 desc=8-way set associative | |l3 desc=8-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR3-1066 | ||
+ | |ecc=No | ||
+ | |max mem=8 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=15.88 GiB/s | ||
+ | |bandwidth schan=7.942 GiB/s | ||
+ | |bandwidth dchan=15.88 GiB/s | ||
+ | |pae=36 bit | ||
}} | }} |
Revision as of 02:42, 1 December 2016
Template:mpu Celeron P4600 is a 64-bit dual-core x86 mobile microprocessor introduced by Intel in 2010. This processor operates at a frequency of 2.00 GHz and a TDP of 35 W. This MPU is manufactured on a 32 nm process based on the Westmere microarchitecture (Arrandale core). This processor incorporated the HD Graphics (Ironlake) IGP on the same package operating at a base frequency of 500.00 MHz and a burst frequency of 667.00 MHz.
Cache
- Main article: Westmere § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Facts about "Celeron P4600 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Celeron P4600 - Intel#package + and Celeron P4600 - Intel#io + |
base frequency | 1,999.99 MHz (2 GHz, 1,999,990 kHz) + |
bus links | 1 + |
bus rate | 2,500 MT/s (2.5 GT/s, 2,500,000 kT/s) + |
bus type | DMI 1.0 + |
chipset | Ibex Peak + |
clock multiplier | 15 + |
core count | 2 + |
core family | 6 + |
core model | 37 + |
core name | Arrandale + |
core stepping | K0 + |
cpuid | 0x20655 + |
designer | Intel + |
device id | 0x0046 + |
die area | 81 mm² (0.126 in², 0.81 cm², 81,000,000 µm²) + |
family | Celeron + |
first announced | March 28, 2010 + |
first launched | March 28, 2010 + |
full page name | intel/celeron/p4600 + |
has ecc memory support | false + |
has extended page tables support | true + |
has feature | Enhanced SpeedStep Technology +, Extended Page Tables + and Flex Memory Access + |
has intel enhanced speedstep technology | true + |
has intel flex memory access support | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics (Ironlake) + |
integrated gpu base frequency | 500 MHz (0.5 GHz, 500,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 12 + |
integrated gpu max frequency | 667 MHz (0.667 GHz, 667,000 KHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
l3$ description | 8-way set associative + |
l3$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
ldate | March 28, 2010 + |
manufacturer | Intel + |
market segment | Mobile + |
max cpu count | 1 + |
max junction temperature | 363.15 K (90 °C, 194 °F, 653.67 °R) + |
max memory | 8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) + |
max memory bandwidth | 15.88 GiB/s (16,261.12 MiB/s, 17.051 GB/s, 17,051.02 MB/s, 0.0155 TiB/s, 0.0171 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 16 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Westmere + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | P4600 + |
name | Intel Celeron P4600 + |
package | rPGA-988A + |
part number | CP80617005307AB + |
platform | Calpella + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |
s-spec | SLBZY + |
series | P4000 + |
smp max ways | 1 + |
supported memory type | DDR3-1066 + |
tdp | 35 W (35,000 mW, 0.0469 hp, 0.035 kW) + |
technology | CMOS + |
thread count | 2 + |
transistor count | 382,000,000 + |
word size | 64 bit (8 octets, 16 nibbles) + |