Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/xeon e3/e3-1275 v6"
| Line 1: | Line 1: | ||
{{intel title|Xeon E3-1275 v6}} | {{intel title|Xeon E3-1275 v6}} | ||
{{mpu | {{mpu | ||
| + | | future = Yes | ||
| name = Xeon E3-1275 v6 | | name = Xeon E3-1275 v6 | ||
| no image = Yes | | no image = Yes | ||
Revision as of 23:34, 3 December 2016
Template:mpu The Xeon E3-1275 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3.8 GHz, this MPU has a TDP of 78 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Kaby Lake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 4-way set associative (per core, write-back) |
| L3$ | 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB |
shared |
Facts about "Xeon E3-1275 v6 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ description | shared + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |