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Difference between revisions of "intel/xeon e3/e3-1280 v6"
< intel

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{{unknown features}}
 
{{unknown features}}
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== Cache ==
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{{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}}
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{{cache info
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|l1i cache=128 KiB
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|l1i break=4x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=128 KiB
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|l1d break=4x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=1 MiB
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|l2 break=4x256 KiB
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|l2 desc=4-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=8 MiB
 +
|l3 desc=shared
 +
}}

Revision as of 23:20, 5 November 2016

Template:mpu The Xeon E3-1280 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3.9 GHz, this MPU has a TDP of 74 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Kaby Lake § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 4-way set associative (per core, write-back)
L3$ 8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
shared
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Facts about "Xeon E3-1280 v6 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ descriptionshared +
l3$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +