Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e3/e3-1245 v6"
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| s-spec qs = | | s-spec qs = | ||
| cpuid = | | cpuid = | ||
| + | |||
| + | | microarch = Kaby Lake | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | process = 14 nm | ||
| + | | transistors = | ||
| + | | technology = CMOS | ||
| + | | die size = | ||
| + | | word size = 64 bit | ||
| + | | core count = 4 | ||
| + | | thread count = 8 | ||
| + | | max cpus = 1 | ||
| + | | max memory = | ||
| electrical = | | electrical = | ||
Revision as of 23:16, 5 November 2016
Template:mpu The Xeon E3-1245 v6 is a 64-bit quad-core x86 microprocessor set to be introduced by Intel in late 2016 or early 2017. Operating at 3.7 GHz, this MPU has a TDP of 78 W. This processor is a Kaby Lake-based chip and is manufactured on a Intel's 14 nm process.
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Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |