From WikiChip
Difference between revisions of "intel/xeon e5/e5-2689 v4"
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| cpuid = 406F1 | | cpuid = 406F1 | ||
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| microarch = Broadwell | | microarch = Broadwell | ||
| platform = Grantley EP 2S | | platform = Grantley EP 2S |
Revision as of 15:22, 4 December 2016
Template:mpu The Xeon E5-2689 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for standard 2S environments. Operating at 3.1 GHz with a turbo boost frequency of 3.8 GHz for a single active core, this MPU has a TDP of 165 W and is manufactured on a 14 nm process (based on Broadwell).
Cache
- Main article: Broadwell § Cache
Cache Info [Edit Values] | ||
L1I$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 320 KiB 327,680 B 0.313 MiB |
10x32 KiB 8-way set associative (per core, write-back) |
L2$ | 2.5 MiB 2,560 KiB 2,621,440 B 0.00244 GiB |
10x256 KiB 8-way set associative (per core, write-back) |
L3$ | 25 MiB 25,600 KiB 26,214,400 B 0.0244 GiB |
10x2.5 MiB 20-way set associative (shared, per core, write-back) |
Graphics
This microprocessor has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller | |
Type | DDR4-2400 |
Controllers | 1 |
Channels | 4 |
ECC Support | Yes |
Max bandwidth | 71.53 GiB/s |
Bandwidth (single) | 17.88 GiB/s |
Bandwidth (dual) | 35.76 GiB/s |
Max memory | 1,536 GiB |
Physical Address Extensions | 46 bit |
Expansions
Features
Facts about "Xeon E5-2689 v4 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) + |
l3$ description | 20-way set associative + |
l3$ size | 25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) + |