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Difference between revisions of "intel/xeon e5/e5-2618l v4"
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| socket 0 type      = LGA
 
| socket 0 type      = LGA
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}}
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The '''Xeon E5-2618L v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
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== Cache ==
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
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{{cache info
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|l1i cache=320 KiB
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|l1i break=10x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=320 KiB
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|l1d break=10x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=2.5 MiB
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|l2 break=10x256 KiB
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|l2 desc=8-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=25 MiB
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|l3 break=10x2.5 MiB
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|l3 desc=20-way set associative
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|l3 extra=(shared, per core, write-back)
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}}
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== Graphics ==
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This microprocessor has no [[integrated graphics processing unit]].
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== Memory controller ==
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{{integrated memory controller
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| type              = DDR4-2133
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| controllers        = 1
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| channels          = 4
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| ecc support        = Yes
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| max bandwidth      = 63.58 GiB/s
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| bandwidth schan    = 15.89 GiB/s
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| bandwidth dchan    = 31.79 GiB/s
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| max memory        = 1,536 GiB
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| pae                = 46 bit
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}}
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== Expansions ==
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{{mpu expansions
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| pcie revision      = 3.0
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| pcie lanes        = 40
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| pcie config        = x4
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| pcie config 1      = x8
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| pcie config 2      = x16
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}}
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== Features ==
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{{mpu features
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| em64t      = Yes
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| nx          = Yes
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| txt        = Yes
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| tsx        = Yes
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| vpro        = Yes
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| ht          = Yes
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| tbt1        =
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| tbt2        = Yes
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| tbmt3      =
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| bpt        =
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| vt-x        = Yes
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| vt-d        = Yes
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| ept        = Yes
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| mmx        = Yes
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| sse        = Yes
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| sse2        = Yes
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| sse3        = Yes
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| ssse3      = Yes
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| sse4.1      = Yes
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| sse4.2      = Yes
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| aes        = Yes
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| pclmul      = Yes
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| avx        = Yes
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| avx2        = Yes
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| bmi        = Yes
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| bmi1        = Yes
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| bmi2        = Yes
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| f16c        = Yes
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| fma3        = Yes
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| mpx        =
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| sgx        =
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| eist        = Yes
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| secure key  = Yes
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| os guard    = Yes
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| intel at    =
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| intel ipt  =
 
}}
 
}}

Revision as of 23:23, 4 November 2016

Template:mpu The Xeon E5-2618L v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for low-power 2S environments (1U square form factor). Operating at 2.2 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 75 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L1D$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L2$ 2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
10x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Memory controller

Integrated Memory Controller
Type DDR4-2133
Controllers 1
Channels 4
ECC Support Yes
Max bandwidth 63.58 GiB/s
Bandwidth (single) 15.89 GiB/s
Bandwidth (dual) 31.79 GiB/s
Max memory 1,536 GiB
Physical Address Extensions 46 bit

Expansions

Template:mpu expansions

Features

Template:mpu features

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Facts about "Xeon E5-2618L v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +