From WikiChip
Difference between revisions of "intel/xeon e5/e5-2660 v4"
< intel‎ | xeon e5

(gpu)
Line 105: Line 105:
 
|l3 extra=(shared, per core, write-back)
 
|l3 extra=(shared, per core, write-back)
 
}}
 
}}
 +
 +
== Graphics ==
 +
This microprocessor has no [[integrated graphics processing unit]].

Revision as of 12:30, 3 November 2016

Template:mpu The Xeon E5-2660 v4 is a 64-bit tetradeca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for advanced 2S environments. Operating at 2 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L1D$ 448 KiB
458,752 B
0.438 MiB
14x32 KiB 8-way set associative (per core, write-back)
L2$ 3.5 MiB
3,584 KiB
3,670,016 B
0.00342 GiB
14x256 KiB 8-way set associative (per core, write-back)
L3$ 35 MiB
35,840 KiB
36,700,160 B
0.0342 GiB
14x2.5 MiB 20-way set associative (shared, per core, write-back)

Graphics

This microprocessor has no integrated graphics processing unit.

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-2660_v4&oldid=26552"
Facts about "Xeon E5-2660 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size448 KiB (458,752 B, 0.438 MiB) +
l1i$ description8-way set associative +
l1i$ size448 KiB (458,752 B, 0.438 MiB) +
l2$ description8-way set associative +
l2$ size3.5 MiB (3,584 KiB, 3,670,016 B, 0.00342 GiB) +
l3$ description20-way set associative +
l3$ size35 MiB (35,840 KiB, 36,700,160 B, 0.0342 GiB) +