From WikiChip
Difference between revisions of "intel/xeon e5/e5-1620 v4"
< intel‎ | xeon e5

(+cache)
Line 84: Line 84:
 
}}
 
}}
 
The '''Xeon E5-1620 v4''' is a {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.5 GHz with a {{intel|turbo boost}} frequency of 3.8 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-1620 v4''' is a {{arch|64}} [[quad-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.5 GHz with a {{intel|turbo boost}} frequency of 3.8 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 +
 +
== Cache ==
 +
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
 +
{{cache info
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1i extra=(per core, write-back)
 +
|l1d cache=128 KiB
 +
|l1d break=4x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d extra=(per core, write-back)
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l2 desc=8-way set associative
 +
|l2 extra=(per core, write-back)
 +
|l3 cache=10 MiB
 +
|l3 break=4x2.5 MiB
 +
|l3 desc=20-way set associative
 +
|l3 extra=(shared, per core, write-back)
 +
}}

Revision as of 11:29, 3 November 2016

Template:mpu The Xeon E5-1620 v4 is a 64-bit quad-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for 1S workstations. Operating at 3.5 GHz with a turbo boost frequency of 3.8 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L1D$ 128 KiB
131,072 B
0.125 MiB
4x32 KiB 8-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
4x256 KiB 8-way set associative (per core, write-back)
L3$ 10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
4x2.5 MiB 20-way set associative (shared, per core, write-back)
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_e5/e5-1620_v4&oldid=26526"
Facts about "Xeon E5-1620 v4 - Intel"
RDF feed
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
l3$ description20-way set associative +
l3$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +