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Difference between revisions of "intel/xeon e5/e5-4610 v4"
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The '''Xeon E5-4610 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no {{intel|turbo boost}}, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-4610 v4''' is a {{arch|64}} [[deca-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no {{intel|turbo boost}}, this MPU has a TDP of 105 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
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== Cache ==
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{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
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{{cache info
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|l1i cache=320 KiB
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|l1i break=10x32 KiB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=320 KiB
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|l1d break=10x32 KiB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=2.5 MiB
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|l2 break=10x256 KiB
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|l2 desc=8-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=25 MiB
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|l3 break=10x2.5 MiB
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|l3 desc=20-way set associative
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|l3 extra=(shared, per core, write-back)
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}}

Revision as of 11:09, 3 November 2016

Template:mpu The Xeon E5-4610 v4 is a 64-bit deca-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for basic 4S environments. Operating at base frequency of 1.8 GHz with no turbo boost, this MPU has a TDP of 105 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L1D$ 320 KiB
327,680 B
0.313 MiB
10x32 KiB 8-way set associative (per core, write-back)
L2$ 2.5 MiB
2,560 KiB
2,621,440 B
0.00244 GiB
10x256 KiB 8-way set associative (per core, write-back)
L3$ 25 MiB
25,600 KiB
26,214,400 B
0.0244 GiB
10x2.5 MiB 20-way set associative (shared, per core, write-back)
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Facts about "Xeon E5-4610 v4 - Intel"
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l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description8-way set associative +
l2$ size2.5 MiB (2,560 KiB, 2,621,440 B, 0.00244 GiB) +
l3$ description20-way set associative +
l3$ size25 MiB (25,600 KiB, 26,214,400 B, 0.0244 GiB) +