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Difference between revisions of "intel/xeon e5/e5-4655 v4"
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|l1d extra=(per core, write-back)
 
|l1d extra=(per core, write-back)
 
|l2 cache=4 MiB
 
|l2 cache=4 MiB
−
|l2 break=16x256 KiB
+
|l2 break=8x256 KiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
|l2 extra=(per core, write-back)
 
|l2 extra=(per core, write-back)
−
|l3 cache=40 MiB
+
|l3 cache=30 MiB
−
|l3 break=16x2.5 MiB
+
|l3 break=8x3.75 MiB
 
|l3 desc=20-way set associative
 
|l3 desc=20-way set associative
 
|l3 extra=(shared, per core, write-back)
 
|l3 extra=(shared, per core, write-back)
 
}}
 
}}

Revision as of 03:39, 3 November 2016

Template:mpu The Xeon E5-4655 v4 is a 64-bit octa-core x86 microprocessor introduced by Intel in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a turbo boost frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a 14 nm process (based on Broadwell).

Cache

Main article: Broadwell § Cache
Cache Info [Edit Values]
L1I$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L1D$ 256 KiB
262,144 B
0.25 MiB
8x32 KiB 8-way set associative (per core, write-back)
L2$ 4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
8x256 KiB 8-way set associative (per core, write-back)
L3$ 30 MiB
30,720 KiB
31,457,280 B
0.0293 GiB
8x3.75 MiB 20-way set associative (shared, per core, write-back)
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Facts about "Xeon E5-4655 v4 - Intel"
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l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description20-way set associative +
l3$ size30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +