From WikiChip
Difference between revisions of "amd/duron/dhm1000avs1b"
< amd‎ | duron

Line 80: Line 80:
 
}}
 
}}
 
The '''Mobile Duron 1000''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in late 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 1000 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.
 
The '''Mobile Duron 1000''' based on the {{amd|Morgan|l=core}} (Camaro) core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in late 2001. This model was part of the second generation of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} on a [[180 nm process]], this MPU operated at 1000 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 +
{{cache info
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Features ==
 +
{{mpu features
 +
| em64t      =
 +
| nx          =
 +
| txt        =
 +
| tsx        =
 +
| vpro        =
 +
| ht          =
 +
| tbt1        =
 +
| tbt2        =
 +
| bpt        =
 +
| vt-x        =
 +
| vt-d        =
 +
| ept        =
 +
| mmx        = Yes
 +
| emmx        = Yes
 +
| 3dnow      = Yes
 +
| e3dnow      = Yes
 +
| sse        = Yes
 +
| sse2        =
 +
| sse3        =
 +
| ssse3      =
 +
| sse4        =
 +
| sse4.1      =
 +
| sse4.2      =
 +
| aes        =
 +
| pclmul      =
 +
| avx        =
 +
| avx2        =
 +
| bmi        =
 +
| bmi1        =
 +
| bmi2        =
 +
| f16c        =
 +
| fma3        =
 +
| mpx        =
 +
| sgx        =
 +
| eist        =
 +
}}
 +
* [[has feature::Halt State]]
 +
* [[has feature::Sleep State]]
 +
 +
== See also ==
 +
* {{amd|Duron}}
 +
* {{intel|Celeron}}

Revision as of 14:57, 23 October 2016

Template:mpu The Mobile Duron 1000 based on the Morgan (Camaro) core was a 32-bit x86 microprocessor developed by AMD and introduced in late 2001. This model was part of the second generation of the Duron family. Designed based on AMD's K7 on a 180 nm process, this MPU operated at 1000 MHz with a bus capable of 200 MT/s with a max TDP of 25 W.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/dhm1000avs1b&oldid=26111"
Facts about "Duron 1000 (Camaro) - AMD"
RDF feed
has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +