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Difference between revisions of "intel/core i5/i5-7400"
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+ | == Cache == | ||
+ | {{main|intel/microarchitectures/kaby lake#Memory_Hierarchy|l1=Kaby Lake § Cache}} | ||
+ | {{cache info | ||
+ | |l1i cache=128 KiB | ||
+ | |l1i break=4x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1i extra=(per core, write-back) | ||
+ | |l1d cache=128 KiB | ||
+ | |l1d break=4x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d extra=(per core, write-back) | ||
+ | |l2 cache=1 MiB | ||
+ | |l2 break=4x256 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | |l2 extra=(per core, write-back) | ||
+ | |l3 cache=6 MiB | ||
+ | |l3 desc=shared | ||
+ | }} |
Revision as of 22:16, 22 September 2016
Template:mpu The Core i5-7400 is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016. This MPU operates at 3 GHz with a TDP of 65 W.
Cache
- Main article: Kaby Lake § Cache
Cache Info [Edit Values] | ||
L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 4-way set associative (per core, write-back) |
L3$ | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB |
shared |
Facts about "Core i5-7400 - Intel"
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ description | shared + |
l3$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |