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Difference between revisions of "intel/core i5/i5-7400t"
(Created page with "{{intel title|Core i5-7400T}} The '''Core i5-7400T''' is a {{arch|64}} x86 quad-core microprocessor based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by...") |
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{{intel title|Core i5-7400T}} | {{intel title|Core i5-7400T}} | ||
| + | {{mpu | ||
| + | | name = Core i5-7400T | ||
| + | | no image = yes | ||
| + | | image = | ||
| + | | image size = | ||
| + | | caption = | ||
| + | | designer = Intel | ||
| + | | manufacturer = Intel | ||
| + | | model number = i5-7400T | ||
| + | | part number = | ||
| + | | part number 1 = | ||
| + | | part number 2 = | ||
| + | | part number 3 = | ||
| + | | market = Desktop | ||
| + | | first announced = | ||
| + | | first launched = | ||
| + | | last order = | ||
| + | | last shipment = | ||
| + | |||
| + | | family = Core i5 | ||
| + | | series = | ||
| + | | locked = Yes | ||
| + | | frequency = 2,400 MHz | ||
| + | | turbo frequency = | ||
| + | | turbo frequency1 = | ||
| + | | turbo frequency2 = | ||
| + | | turbo frequency3 = | ||
| + | | turbo frequency4 = | ||
| + | | turbo frequency5 = | ||
| + | | turbo frequency6 = | ||
| + | | turbo frequency7 = | ||
| + | | turbo frequency8 = | ||
| + | | bus type = DMI 3.0 | ||
| + | | bus speed = | ||
| + | | bus rate = 8 GT/s | ||
| + | | clock multiplier = 24 | ||
| + | | s-spec = | ||
| + | | s-spec 2 = | ||
| + | | s-spec N = | ||
| + | | s-spec es = | ||
| + | | s-spec es 2 = | ||
| + | | s-spec es N = | ||
| + | | s-spec qs = | ||
| + | | s-spec qs 2 = | ||
| + | | s-spec qs N = | ||
| + | | cpuid = | ||
| + | | cpuid 2 = | ||
| + | |||
| + | | microarch = Kaby Lake | ||
| + | | platform = | ||
| + | | chipset = | ||
| + | | core name = Kaby Lake S | ||
| + | | core family = | ||
| + | | core model = | ||
| + | | core stepping = | ||
| + | | core stepping 2 = | ||
| + | | core stepping N = | ||
| + | | process = 14 nm | ||
| + | | transistors = | ||
| + | | technology = CMOS | ||
| + | | die area = | ||
| + | | die width = | ||
| + | | die length = | ||
| + | | word size = 32 bit | ||
| + | | core count = 4 | ||
| + | | thread count = 4 | ||
| + | | max cpus = 1 | ||
| + | | max memory = 64 GB | ||
| + | | max memory addr = | ||
| + | |||
| + | | electrical = Yes | ||
| + | | power = | ||
| + | | v core = | ||
| + | | v core tolerance = | ||
| + | | v io = | ||
| + | | v io tolerance = | ||
| + | | sdp = | ||
| + | | tdp = 35 W | ||
| + | | temp min = | ||
| + | | temp max = | ||
| + | | tjunc min = | ||
| + | | tjunc max = | ||
| + | | tcase min = 0 °C | ||
| + | | tcase max = 66 °C | ||
| + | | tstorage min = | ||
| + | | tstorage max = | ||
| + | |||
| + | | packaging = Yes | ||
| + | | package = FCLGA-1151 | ||
| + | | package type = FCLGA | ||
| + | | package pitch = 0.914 mm | ||
| + | | package size = 37.5 mm x 37.5 mm | ||
| + | | socket = LGA-1151 | ||
| + | | socket type = LGA | ||
| + | }} | ||
The '''Core i5-7400T''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W. | The '''Core i5-7400T''' is a {{arch|64}} [[x86]] [[quad-core microprocessor]] based on {{intel|Kaby Lake|l=arch}} and is set to be introduced by [[Intel]] in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W. | ||
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| + | |||
| + | {{unknown features}} | ||
Revision as of 22:12, 22 September 2016
Template:mpu The Core i5-7400T is a 64-bit x86 quad-core microprocessor based on Kaby Lake and is set to be introduced by Intel in late 2016. This MPU operates at 2.4 GHz with a TDP of 35 W.