Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i3/6120t"
(→Cache) |
|||
| Line 35: | Line 35: | ||
| s-spec = SR2HF | | s-spec = SR2HF | ||
| + | | isa family = x86 | ||
| + | | isa = x86-64 | ||
| microarch = Skylake | | microarch = Skylake | ||
| platform = | | platform = | ||
Revision as of 15:21, 9 December 2016
Template:mpu
Core i3-6120T is a 64-bit dual-core low-end performance microprocessor set to be introduced by Intel in 2016.
 |
Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release. |
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 64 KiB 65,536 B 0.0625 MiB |
2x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 512 KiB 0.5 MiB 524,288 B 4.882812e-4 GiB |
2x256 KiB 4-way set associative (per core, write-back) |
| L3$ | 3 MiB 3,072 KiB 3,145,728 B 0.00293 GiB |
shared |
Expansions
Features
Facts about "Core i3-6120T - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
| l3$ description | shared + |
| l3$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |