From WikiChip
Difference between revisions of "amd/k6-iii+/amd-k6-iiie+-500anz"
< amd‎ | k6-iii+

(Created page with "{{amd title|AMD-K6-IIIE+/500ANZ}} {{mpu | name = AMD-K6-IIIE+/500ANZ | no image = Yes | image = | image size = | caption...")
 
Line 82: Line 82:
 
}}
 
}}
 
'''AMD-K6-IIIE+/500ANZ''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W.
 
'''AMD-K6-IIIE+/500ANZ''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}}
 +
[[L3$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip.
 +
{{cache info
 +
|l1i cache=32 KB
 +
|l1i break=1x32 KB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=32 KB
 +
|l1d break=1x32 KB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=256 KB
 +
|l2 break=1x256
 +
|l2 desc=4-way set associative
 +
|l2 extra=(shared)
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Features ==
 +
{{mpu features
 +
| mmx        = Yes
 +
| emmx        = Yes
 +
| 3dnow      = Yes
 +
| e3dnow      = Yes
 +
| pownow      = Yes
 +
}}
 +
* Auto-power down state
 +
* Stop clock state
 +
* Halt state

Revision as of 19:11, 9 September 2016

Template:mpu AMD-K6-IIIE+/500ANZ is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 500 MHz with a bus of 100 MHz and a multiplier of 5. This chip had a TDP of 14.5 W.

Cache

Main article: K6-III § Cache

L3$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L3$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x32 KB 2-way set associative
L2$ 256 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x256 4-way set associative (shared)

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state
  • Halt state
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-iii%2B/amd-k6-iiie%2B-500anz&oldid=24625"
Facts about "AMD-K6-IIIE+/500ANZ - AMD"
RDF feed
base frequency499.99 MHz (0.5 GHz, 499,990 kHz) +
bus rate99.99 MT/s (0.1 GT/s, 99,990 kT/s) +
bus speed99.99 MHz (0.1 GHz, 99,990 kHz) +
bus typeFSB +
clock multiplier5 +
core count1 +
core family5 +
core model13 +
core stepping0 +, 1 +, 2 + and 3 +
core voltage1.8 V (18 dV, 180 cV, 1,800 mV) +
core voltage tolerance0.1 V +
cpuid5D0 +
designerAMD +
familyK6-III+ +
first announcedSeptember 25, 2000 +
first launchedSeptember 25, 2000 +
full page nameamd/k6-iii+/amd-k6-iiie+-500anz +
instance ofmicroprocessor +
io voltage3.368 V (33.675 dV, 336.75 cV, 3,367.5 mV) +
io voltage tolerance7% +
l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description4-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateSeptember 25, 2000 +
manufacturerAMD +
market segmentEmbedded +
max case temperature358.15 K (85 °C, 185 °F, 644.67 °R) +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max storage temperature423.15 K (150 °C, 302 °F, 761.67 °R) +
microarchitectureK6-III +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature208.15 K (-65 °C, -85 °F, 374.67 °R) +
model numberAMD-K6-IIIE+/500ANZ +
nameAMD-K6-IIIE+/500ANZ +
part numberAMD-K6-IIIE+/500ANZ +
platformSuper 7 +
process180 nm (0.18 μm, 1.8e-4 mm) +
seriesK6-III+ Embedded +
smp max ways1 +
tdp14.5 W (14,500 mW, 0.0194 hp, 0.0145 kW) +
technologyCMOS +
thread count1 +
transistor count21,400,000 +
word size32 bit (4 octets, 8 nibbles) +