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Difference between revisions of "princeton/piton"
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(Created page with "{{princeton title|Piton}} '''Piton''' is a {{arch|64}} many-core microprocessor developed by Princeton's Parallel Computing Group and announced in August of 2016. The...")
 
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{{princeton title|Piton}}
 
{{princeton title|Piton}}
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'''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}).
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{{mpu
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| name                = Piton
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| no image            =
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| image              = Princeton piton.png
 +
| image size          =
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| caption            = Piton face
 +
| designer            = Princeton
 +
| manufacturer        = IBM
 +
| model number        =
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| part number        =
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| market              = Server
 +
| first announced    = August 23, 2016
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| first launched      =
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| last order          =
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| last shipment      =
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| family              =
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| series              =
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| locked              =
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| frequency          = 1000 MHz
 +
| bus type            =
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| bus speed          = 350 MHz
 +
| bus rate            = 2,800 MT/s
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| clock multiplier    = 2.85
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| cpuid              =
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| cpuid 2            =
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| microarch          =
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| platform            =
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| chipset            =
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| core name          =
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| core family        =
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| core model          =
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| core stepping      =
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| process            = 32 nm
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| transistors        = 460,000,000
 +
| technology          = CMOS
 +
| die size            = 36mm²
 +
| word size          = 64 bit
 +
| core count          = 25
 +
| thread count        = 50
 +
| max cpus            =
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| max memory          =
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| max memory addr    =
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| electrical          = Yes
 +
| power              =
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| v core              = 0.9 V
 +
| v core tolerance    =
 +
| v io                =
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| v io tolerance      =
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| sdp                =
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| tdp                =
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| ctdp down          =
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| ctdp down frequency =
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| ctdp up            =
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| ctdp up frequency  =
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| temp min            =
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| temp max            =
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| tjunc min          =
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| tjunc max          =
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| tcase min          =
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| tcase max          =
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| tstorage min        =
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| tstorage max        =
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 +
| packaging          = Yes
 +
| package 0          = QFP-208
 +
| package 0 type      = QFP
 +
| package 0 pins      = 208
 +
| package 0 pitch    = 0.5 mm
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| package 0 width    = 30.60 mm
 +
| package 0 length    = 30.60 mm
 +
| package 0 height    = 3.75 mm
 +
| socket 0            = QFP-208
 +
| socket 0 type      = QFP
 +
}}
 +
'''Piton''' is a {{arch|64}} [[many-core microprocessor]] developed by [[Princeton]]'s Parallel Computing Group and announced in August of 2016. The [[massively parallel processor array|MPPA]] chip contains 25 modified [[OpenSPARC T1]] cores (an implementation of {{sparc|V9|SPARC V9}}). The chip, which was manufactured on [[IBM]]'s [[32 nm|32 nm SOI process]], operates at 1 GHz. The chip was presented On August 32 2016 at the [[Hot Chips]] 28.

Revision as of 21:15, 28 August 2016

Template:mpu Piton is a 64-bit many-core microprocessor developed by Princeton's Parallel Computing Group and announced in August of 2016. The MPPA chip contains 25 modified OpenSPARC T1 cores (an implementation of SPARC V9). The chip, which was manufactured on IBM's 32 nm SOI process, operates at 1 GHz. The chip was presented On August 32 2016 at the Hot Chips 28.

Retrieved from "https://en.wikichip.org/w/index.php?title=princeton/piton&oldid=23750"
Facts about "Piton - Princeton"
RDF feed
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
bus rate2,800 MT/s (2.8 GT/s, 2,800,000 kT/s) +
bus speed350 MHz (0.35 GHz, 350,000 kHz) +
clock multiplier2.85 +
core count25 +
core voltage0.9 V (9 dV, 90 cV, 900 mV) +
designerPrinceton +
die area36 mm² (0.0558 in², 0.36 cm², 36,000,000 µm²) +
die length6 mm (0.6 cm, 0.236 in, 6,000 µm) +
die width6 mm (0.6 cm, 0.236 in, 6,000 µm) +
first announcedAugust 23, 2016 +
full page nameprinceton/piton +
instance ofmicroprocessor +
l1d$ description4-way set associative +
l1d$ size200 KiB (204,800 B, 0.195 MiB) +
l2$ description4-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
ldateAugust 23, 2016 +
main imageFile:Princeton piton.png +
main image captionPiton face +
manufacturerIBM +
market segmentServer +
max cpu count20,000 +
namePiton +
process32 nm (0.032 μm, 3.2e-5 mm) +
smp max ways20,000 +
technologyCMOS +
thread count50 +
transistor count460,000,000 +
word size64 bit (8 octets, 16 nibbles) +