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Difference between revisions of "amd/duron/d650ast1b"
< amd‎ | duron

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{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{cache info
 
{{cache info
−
|l1i cache=64 KB
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|l1i cache=64 KiB
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|l1i break=1x64 KB
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|l1i break=1x64 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
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|l1d cache=64 KB
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|l1d cache=64 KiB
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|l1d break=1x64 KB
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|l1d break=1x64 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=
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|l2 cache=64 KB
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|l2 cache=64 KiB
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|l2 break=1x64 KB
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|l2 break=1x64 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=
 
|l2 extra=

Revision as of 22:48, 20 September 2016

Template:mpu Duron 650 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2000. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 650 MHz with a bus capable of 200 MT/s with a TDP of 24.3 W.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/duron/d650ast1b&oldid=25596"
Facts about "Duron 650 (Spitfire) - AMD"
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has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +