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Difference between revisions of "amd/duron/d850aut1b"
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'''Duron 850''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 850 MHz with a bus capable of 200 MT/s with a typical TDP of 37.4 W. | '''Duron 850''' based on the Spitfire core was a {{arch|32}} [[x86]] [[microprocessor]] developed by [[AMD]] and introduced in 2001. This model was part of the first series of the {{amd|Duron}} family. Designed based on AMD's {{amd|microarchitecture/k7|K7}} (a {{amd|Thunderbird}}-derivative) on a [[180 nm process]], this MPU operated at 850 MHz with a bus capable of 200 MT/s with a typical TDP of 37.4 W. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}} | ||
| + | {{cache info | ||
| + | |l1i cache=64 KB | ||
| + | |l1i break=1x64 KB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=64 KB | ||
| + | |l1d break=1x64 KB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache=64 KB | ||
| + | |l2 break=1x64 KB | ||
| + | |l2 desc=16-way set associative | ||
| + | |l2 extra= | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{mpu features | ||
| + | | em64t = | ||
| + | | nx = | ||
| + | | txt = | ||
| + | | tsx = | ||
| + | | vpro = | ||
| + | | ht = | ||
| + | | tbt1 = | ||
| + | | tbt2 = | ||
| + | | bpt = | ||
| + | | vt-x = | ||
| + | | vt-d = | ||
| + | | ept = | ||
| + | | mmx = Yes | ||
| + | | emmx = Yes | ||
| + | | 3dnow = Yes | ||
| + | | e3dnow = Yes | ||
| + | | sse = | ||
| + | | sse2 = | ||
| + | | sse3 = | ||
| + | | ssse3 = | ||
| + | | sse4 = | ||
| + | | sse4.1 = | ||
| + | | sse4.2 = | ||
| + | | aes = | ||
| + | | pclmul = | ||
| + | | avx = | ||
| + | | avx2 = | ||
| + | | bmi = | ||
| + | | bmi1 = | ||
| + | | bmi2 = | ||
| + | | f16c = | ||
| + | | fma3 = | ||
| + | | mpx = | ||
| + | | sgx = | ||
| + | | eist = | ||
| + | }} | ||
| + | * [[has feature::Halt State]] | ||
| + | * [[has feature::Sleep State]] | ||
Revision as of 00:08, 23 August 2016
Template:mpu Duron 850 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 850 MHz with a bus capable of 200 MT/s with a typical TDP of 37.4 W.
Cache
- Main article: K7 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
1x64 KB 2-way set associative |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
1x64 KB 2-way set associative |
| L2$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
1x64 KB 16-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Halt State
- Sleep State
Facts about "Duron 850 (Spitfire) - AMD"
| has feature | Halt State + and Sleep State + |
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 16-way set associative + |