Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-2/k6-2-300bnz"
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| part number 3 = | | part number 3 = | ||
| market = Mobile | | market = Mobile | ||
| − | | first announced = March, 1999 | + | | first announced = March 22, 1999 |
| − | | first launched = March, 1999 | + | | first launched = March 22, 1999 |
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
Revision as of 04:09, 5 August 2016
Template:mpu K6-2/300BNZ was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 100 MHz.
Contents
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KB to 1 MB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Documents
DataSheet
- Mobile AMD-K6-2 Processor Data Sheet; Publication #21896 Revision E/0, May 2000
Facts about "AMD-K6-2/300BNZ - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |