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Difference between revisions of "amd/k5/amd-ssa-5-75abr"
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'''AMD-SSA/5-75ABR''' was a {{arch|32}} [[x86]] microprocessor developed by [[AMD]] and released in [[1996]]. This processor was the first of AMD's brand new {{amd|microarchitectures/k5|K5 microarchitecture}} designed entirely in-house. The chip operated at 75 MHz. | '''AMD-SSA/5-75ABR''' was a {{arch|32}} [[x86]] microprocessor developed by [[AMD]] and released in [[1996]]. This processor was the first of AMD's brand new {{amd|microarchitectures/k5|K5 microarchitecture}} designed entirely in-house. The chip operated at 75 MHz. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | ||
| + | |||
| + | {{cache info | ||
| + | |l1i cache=16 KB | ||
| + | |l1i break=1x16 KB | ||
| + | |l1i desc=4-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=8 KB | ||
| + | |l1d break=1x8 KB | ||
| + | |l1d desc=4-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache= | ||
| + | |l2 break= | ||
| + | |l2 desc= | ||
| + | |l2 extra= | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This SoC has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | * Auto-power down state | ||
| + | * Stop clock state | ||
| + | |||
| + | == See also == | ||
| + | * {{amd|K5}} | ||
Revision as of 01:20, 26 July 2016
Template:mpu AMD-SSA/5-75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This processor was the first of AMD's brand new K5 microarchitecture designed entirely in-house. The chip operated at 75 MHz.
Contents
Cache
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative |
| L1D$ | 8 KB "KB" is not declared as a valid unit of measurement for this property. |
1x8 KB 4-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
See also
Facts about "AMD-SSA/5-75ABR - AMD"
| l1d$ description | 4-way set associative + |
| l1i$ description | 4-way set associative + |